1. Field of the Invention
A method and system are described for improving the test quality of a scan-based BIST.
2. Description of Related Art
The test schemes for scan-based BIST can be classified as either test-per-clock or test-per-scan, see V. D. Agrawal, C. R. Kime, and K. K. Saluja, xe2x80x9cA Tutorial on Built-In Self-Test, Part 2: Applications,xe2x80x9d IEEE Design and Test of Computers, vol. 10, no. 22, pp. 69-77, June 1993. In test-per-clock BIST, a test vector is applied and its response is compressed every clock cycle. The examples of test-per-clock BIST are BILBO-based design, see B. Konemann, J. Mucha, and C. Zwiehoff, xe2x80x9cBuilt-In Logic Block Observation Technique,xe2x80x9d Digest of Papers 1979 Test Conf., pp. 37-41, October 1979 and circular BIST, see Krasniewski and S. Pilarski, xe2x80x9cCircular Self-Test Path: A Low-Cost BIST Technique for VLSI Circuits,xe2x80x9d IEEE Trans. on CAD, vol. 8, no. 1, pp. 46-55, January 1989. In test-per-scan BIST, a test vector is applied and its response is captured into the scan chains only after the test is scanned into the scan chains. The well-known STUMPS architecture, see P. H. Bardell and W. H. McAnney, xe2x80x9cSelf-Testing of Multichip Logic Modules,xe2x80x9d Digest of Papers 1982 Int""l Test Conf., pp. 200-204, November 1982, falls into this category. There are tradeoffs between these two test application schemes in terms of area overhead, performance degradation, and test application time. The test-per-clock BIST typically has shorter test time but incurs higher area and performance overheads than test-per-scan BIST.
PSBIST is proposed to incorporate partial-scan and pseudo-random testing into the scan-based BIST, see C.-J. Lin, Y. Zorian, and S. Bhawmik, xe2x80x9cIntegration of Partial Scan and Built-In Self-Test,xe2x80x9d JETTA, vol. 7, no. 1-2, pp. 125-137, August 1995. The test application scheme of PSBIST is a combination of test-per-clock BIST and test-per-scan BIST. It results in shorter test time without increasing the area and performance overheads comparing to the conventional test-per-scan BIST. This work is based on the PSBIST architecture. Unlike PSBIST (or any other test-per-scan BIST) which always applies a single capture cycle after scanning in a new test pattern, it is proposed to apply multiple capture cycles after each scan sequence. It has been observed that applying a different number of capture cycles per scan can help to detect a different subset of faults. A general test application scheme is now proposedxe2x80x94multiple test sessions with a unique number of capture cycles per scan in each sessionxe2x80x94for PSBIST. A procedure of finding the optimal parameters (i.e. the number of test sessions and the number of capture cycles per scan in each session) of the test scheme for a given circuit is described in detail. The proposed scheme has been implemented and experimented on ISCAS89 benchmark circuits using an industrial scan-based BIST system, psb2. The results presented at the end of this detailed description illustrate the effectiveness of the proposed approach.